1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device including an interface to which a data bus is connected externally.
2. Description of the Background Art
As systems using semiconductor devices operate at higher speed, it is proposed that semiconductor devices, particularly semiconductor memory devices receive data from external units by using data strobe signals which cyclically change in synchronization with the data. The data strobe signal is output from a data transmission side, transmitted on a signal line provided in parallel with a data bus on a printed-circuit board, and input to a semiconductor device which receives the data.
For example, current semiconductor devices, particularly DDR SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories) include one terminal, for transmitting a data strobe signal, for each chip.
FIG. 30 is a waveform chart for illustrating relations between a conventional data strobe signal and data.
Referring to FIG. 30, at a falling edge of a strobe signal STRB at time t1, the L (low) level of a data signal DQ is latched and received by a semiconductor device.
At time t2, at a rising edge of strobe signal STRB, the H (high) level of data signal DQ is latched and received by the semiconductor device.
At time t3, differently from the case of time t2, the L level of data DQ is received at a rising edge of strobe signal STRB. At time t4, differently from the case of time t1, the H level of data DQ is received at a falling edge of strobe signal STRB.
As described above, when there is one data strobe, it is necessary to receive the H (high) data and the L (low) data at a rising edge of the data strobe and similarly receive the H data and the L data even at a falling edge of the data strobe.
Therefore, correct timing is required for both rising and falling edges of the data strobe signal.
Thus, the differential data strobe method is currently proposed to determine data reception timing by using two strobe signals.
FIG. 31 is an operational waveform chart for illustrating data reception using the differential data strobes.
Referring to FIG. 31, the two strobe signals are complementary strobe signals STRB1, STRB2 which are supplied in synchronization with data. In a semiconductor device, the data reception timing is determined at a crossing of the waveforms of complementary strobe signals STRB1, STRB2.
At time t1 when a falling edge of strobe signal SRTB1 and a rising edge of strobe signal SRTB2 cross each other, the L level of data signal DQ is received by the semiconductor device.
Similarly, at time t2 when a rising edge of strobe signal SRTB1 and a falling edge of strobe signal SRTB2 cross each other, the H level of data signal DQ is received by the semiconductor device.
In the differential data strobe method, however, the accuracy of the data strobe signals cannot be maintained to be high due to data skew which is caused by a phenomenon called SSO (Simultaneously Switching Output).
The SSO will be described briefly. In a device having a large number of output terminals such as a semiconductor memory device, simultaneous outputting of H data from the large number of output terminals drops a power supply potential in the device. Thus, the H data to be output may be delayed. When the large number of output terminals simultaneously output L data, a ground potential rises in the device, thereby delaying the L data. Such a phenomenon is called SSO.
FIG. 32 is a diagram for illustrating skew caused by SSO.
Referring to FIG. 32, when a large number of output terminals simultaneously output H data, a power supply potential falls in the device, thereby delaying the H data to be output. When the large number of output terminals simultaneously output L data, a ground potential rises in the device, thereby delaying the L data.
FIG. 33 is a diagram for illustrating the timing margin of data with respect to a strobe signal when the SSO is caused.
Referring to FIG. 33, assume that data signals DQ1 to DQn-1 provide H data and a data signal DQn provides L data at this time. Because of the SSO, data of data signals DQ1 to DQn-1 is determined, delayed by skew TD as compared with data signal DQn. Therefore, data signal DQn falls to the L level at time t1, and data signals DQ1 to DQn-1 rise to the H level at time t2 which is later than time t1 by the skew TD.
Thereafter, a strobe signal DQS for receiving data signals DQ1 to DQn changes at time t3 after fixed delay time Tfd since data signals DQ1 to DQn are determined.
At time t4, data signal DQn then rises from the L level to the H level.
If the SSO skew occurs to a data signal as described above, an effective window capable of causing data to be received using strobe signal DQS is made smaller by the skew TD. Thus, setup time Ts and hold time Th are both made smaller for a strobe signal reception edge.
In other words, the timing for outputting data becomes early or late according to the number of output terminals for outputting data at which data changes. Therefore, even if strobe signals STRB1, SRTB2 are output at correct timing, data is not received correctly unless the data reception timing is delayed in the semiconductor device by an amount of skew TD caused by SSO.
In a conventional system, a device which has an output transistor to pull up a potential at a terminal and an output transistor to pull down a potential at a terminal needs to have the both characteristics equalized. However, the two problems described below make it very difficult to make such adjustment.
First, the circuit characteristics of a pull up transistor and those of a pull down transistor are different from each other. For example, when an N channel MOS transistor is used as an output transistor, it operates mainly in a non-saturation region if it is used for pulling down. However, the N channel MOS transistor operates mainly in a saturation region if it is used for pulling up.
Second, a pull up transistor and a pull down transistor cause mutually different fluctuation according to processes. For example, when a P channel MOS transistor is used for pulling up and an N channel MOS transistor is used for pulling down, manufacturing variation is different between the P channel MOS transistor and the N channel MOS transistor.
In addition, a conventional open drain system has only a pull down transistor, and the rising time is determined by termination resistance. It is therefore very difficult to equalize the delay time of a rise and that of a fall of an output signal.